EDN

DESIGN FLOWS: Engineers write up SystemC TLM concepts

Santa Cruz, Calif. – Claiming to document a major step forward in system-on-chip design, STMicroelectronics engineers are writing a book about the SystemC transaction-level modeling the European ...
Design-Reuse

Modelling OCP Interfaces in SystemC: Standards built on top of OSCI's TLM-2

OSCI has recently published their TLM-2.0 technology which provides for interoperability between SystemC models of electronic components whose primary interfaces are memorymapped busses. This is a ...
Business Wire

IEEE Approves Revised IEEE 1666™ “SystemC Language” Standard for Electronic System-Level Design, Adding Support for Transaction-level Modeling

PISCATAWAY, N.J.--(BUSINESS WIRE)--IEEE, the world's largest professional association advancing technology for humanity, today announced that the IEEE Standards Association (IEEE-SA) Standards Board ...
CIOL

Synopsys supports OSCI SystemC TLM-2.0

MOUNTAIN VIEW, USA: Synopsys Inc. has announced support for the newly ratified Open SystemC Initiative (OSCI) SystemC TLM-2.0 standard in its Innovator and DesignWare System-Level Library products.
Business Wire

Reference Virtual Platform of ARM Model Running Linux Under SystemC/TLM-2.0 Released by Open Virtual Platforms (OVP)

THAME, England--(BUSINESS WIRE)--The Open Virtual Platforms (OVP) initiative (www.OVPworld.org) has announced the release of a reference virtual platform of the ARM Integrator development board using ...
EDN

SystemC standards group releases transaction-level modeling standard

SystemC standards group Open SystemC Initiative (OSCI) has released the SystemC TLM (transaction-level modeling) standard version 1.0. The TLM standard kit, which can be downloaded under an open ...
Design-Reuse

Open SystemC Initiative Announces Proposal for Significant Extensions to Transaction-Level Modeling (TLM) Standard

Milestone Release of Draft TLM 2.0 Kit for Public Review Promotes Interoperability San Jose, Calif. and Grenoble, France (at the ECSI TLM Workshop) – December 4, 2006 – The Open SystemC Initiative ...
Semiconductor Engineering

Interface Additions To The e Language For Effective Communication With SystemC TLM 2.0 Models

The last several years have seen strong adoption of transaction-level models using SystemC TLM 2.0. Those models are used for software validation and virtual prototyping. For functional verification, ...
Semiconductor Engineering

Experts At The Table: The Future Of SystemC

System-Level Design moderated a discussion about the future of SystemC with Thomas Alsop, corporate design solution expert at Intel; Ambar Sarkar, chief verification technologist at Paradigm Works; ...
Electronic Design

Implement Abstraction By Encapsulation In SystemC

High-level design (HLD) represents a hardware design at a more abstract level than register transfer level (RTL). A high-level synthesis (HLS) tool then can be used to produce the RTL necessary to ...
uni

SystemC to Timed Automata Transformation Engine (STATE)

STATE takes a SystemC design as input and transforms it into a corresponding UPPAAL timed automata model. The transformation is based on a formal semantics defined for SystemC in ...